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These inventions relate to the manufacture of high density computer systems using circuit board assemblies having very small pads (4-12 mil) for connection of flip chips and wire bond chips and/or very fine conductors for fan out from ball grid array modules, fine pitch (0.3-0.6 mm spacing) leaded components, flip chips, or wire bond chips that are attached to the circuit board assemblies. These inventions also relate to the manufacture of chip carriers in which flip chips and/or wire bond chips are connected to such very small pads and in which very fine conductors fan out from the chip connection pads to terminals for connection to circuit board assemblies. More specifically these inventions relate to an additive processes in which metal is fully electrolessly deposited onto substrates to form these very fine conductors and very small pads.
The following background is for convenience of those skilled in the art and for incorporating the listed citations by reference. The following background information is not an assertion that a search has been made, or that the following citations are analogous art, or that any of the following citations are pertinent or the only pertinent art that exists, or that any of the following citations are prior art.
The continued introduction of higher I/O and higher density surface mount components especially 0.3-0.6 mm gull wing leaded components, 40 mil ball grid array BGA modules, as well as the direct connection flip chips and wire bond chips to circuit boards, has resulted in a need for very fine conductors on organic circuit boards for fan out at these components. Also, the introduction of connecting flip chips and wire bond chips directly onto organic and metal circuit boards requires very small pads to be reliably formed. Furthermore, the introduction of chip carrier modules with organic and organic coated metal substrates has created a demand for very fine conductors and very small pads on organic surfaces.
Commonly, circuit boards include buried power planes (ground and other voltage levels) and signal planes on the surface. Such wiring layers are separated by layers of fiberglass filled epoxy (FR4 and G10). Connections between wiring layers are formed by drilling holes and plating the holes with copper to form plated through holes (PTHs). The power planes are pre-patterned with openings so that not all PTHs are required to connect to all the power planes. The PTHs and their surrounding lands require substantial surface area which can not be easily reduced because plating requires circulation of fluids in the holes.
More exotic circuit boards include multiple exterior signal wiring layers which may be separated by thin dielectric layers known as thin film. In order to provide higher density of conductors and pads, holes are formed through the thin dielectric layers by photolithography (producing photo vias) and plated to electrically connect between adjacent exterior wiring layers.
In subtractive processing, copper is plated over the entire surface of the substrate and onto the walls of through holes. Usually the copper is provided by electrolessly plating a thin strike layer, then electroplating a thick coating over the strike layer. Then the surface is coated with a photoresist that tents over the through holes, the photoresist is exposed and developed to provide a pattern that covers only the desired copper, and then the exposed copper is etched away to form an exterior wiring layer.
Another commonly used process is partial additive or semi-additive plating. In this process a very thin flash layer of copper is electrolessly deposited over the entire surface and in the through holes. Then the surface is coated with a photoresist which is exposed and developed to provide a pattern that covers the flash layer except the desired wiring pattern. Then copper is electroplated onto the exposed portion of the strike layer, a protective metal may be electroplated over the copper, the photoresist is stripped away, and the exposed flash layer is etched away.
In electroless plating the surface of a substrate is seeded by a catalyst material and then submerged in an electroless plating bath in which copper is chemically plated over the catalyst without providing any external electrical potentials. Deposition by electroless plating requires far more time than electroplating; thus, electroless plating is commonly used only for a thin layer called a flash or strike layer to allow subsequent electroplating.
For providing very fine conductors, full additive electroless copper plating is preferred in order to provide finer conductors and eliminate the risk of tenting failure causing etching away of copper plated in very small photo vias. In one method the surface is seeded, then a photoresist pattern is formed over the surface, a wiring layer is electrolessly formed at openings in the photoresist pattern, the photoresist is stripped and the remaining catalyst is removed. Alternately, the photoresist is deposited and patterned, the seeding layer is deposited over the exposed surface of the substrate and photoresist and then the photoresist is stripped to remove the undesired copper.
Those skilled in the art are directed to the following references. U.S. Pat. No. 4,908,087 to Murooka describes laminating to form a substrate structure. U.S. Pat. No. 3,163,588 to Shortt suggests stripable frisket, seeding and electroplating. U.S. Pat. No. 5,166,037 to Atkinson describes forming wiring layers on circuit board substrates with electroless plating. Printed Circuit Base by Marshall in IBM TDB Vol. 10, No. 5, October 1967, describes a sensitizing material. U.S. Pat. No. 4,590,539 to Sanjana discloses epoxies, fillers, curing agents, and catalysts. U.S. Pat. No. 4,217,182 to Cross, U.S. Pat. No. 4,378,384 to Murakami, U.S. Pat. No. 4,495,216 to Soerensen, U.S. Pat. No. 4,528,245 to Jobbins, U.S. Pat. No. 4,631,117 to Minten, U.S. Pat. No. 4,639,380 to Amelio, U.S. Pat. No. 4,684,550 to Milius, U.S. Pat. No. 4,601,847 to Barber, U.S. Pat. No. 4,820,388 to Kurze, U.S. Pat. No. 4,716,059 to Kim, and U.S. Pat. No. 5,250,105 to Gomes suggests treatment with surfactant before electroless plating. Also, Japanese patent JP 02-22477 to Takita suggests treating with surfactant prior to electroless plating. In the prior art surfactant treatment was followed by applications of catalyst, acid, or rinsing prior to electroless plating. U.S. Pat. No. 4,448,804 to Amelio, U.S. Pat. No. 4,964,948 to Reed, and U.S. Pat. No. 5,348,574 to Tokas suggests methods and materials for seeding a substrate prior to electroless plating. U.S. Pat. No. 5,200,026 to Okabe and U.S. Pat. No. 5,266,446 to Chang suggest processes for forming thin film structures on substrates. U.S. Pat. No. 4,897,338 to Spicciati, U.S. Pat. No. 4,940,651 to Brown, U.S. Pat. No. 5,070,002 to Leech, U.S. Pat. No. 5,300,402 to Card, U.S. Pat. No. 5,427,895 to Magnuson, and U.S. Pat. No. 5,026,624 and U.S. Pat. No. 5,439,779 to Day discuss photoresists.
The proceeding citations are hereby incorporated in whole by reference.
In the inventions of Applicants, a layer of fluid containing surfactant is applied over a catalyst layer on a substrate and the wet substrate is treated in an electroless bath. The level of surfactant in the bath is approximately ascertained by determining the surface tension of the electroless solution and surfactant is metered into the bath depending on the determination of surface tension.
The invention reduces the number of voids in a full electroless additive circuitization of small features which allows very fine line widths and very small pad sizes to be reliably formed. The invention allows flip chip and wire bond pads to be reliably formed on organic surfaced component substrates and also on organic surfaced circuit board substrates to greatly increase device density on the circuit board. The invention includes circuit boards made by the process of the invention in which surface mount components may be placed at a higher density to allow reduced signal flight times and faster circuit board speeds. Furthermore, the invention includes a computer system which operates faster due to the shorter signal flight times which result from the higher wiring densities of the invention.
Other features and advantages of this invention will become apparent from the following detailed description of the presently preferred embodiments of the invention illustrated by these drawings.